Method of forming a semiconductor device using a carbon doped oxide layer to control the chemical mechanical polishing of a dielectric layer

ABSTRACT

A method for making a semiconductor device is described. That method comprises forming a carbon doped oxide containing layer and a dielectric layer on a substrate, such that at least part of the dielectric layer is located above at least part of the carbon doped oxide containing layer. A chemical mechanical polishing process is then applied to remove the part of the dielectric layer that is located above the part of the carbon doped oxide containing layer, such that it removes the dielectric layer at a significantly faster rate than it can remove the carbon doped oxide containing layer.

FIELD OF THE INVENTION

[0001] The present invention relates to methods for making semiconductordevices, in particular, those that apply a chemical mechanical polishingprocess to planarize a dielectric layer.

BACKGROUND OF THE INVENTION

[0002] When making semiconductor devices, dielectric layers are used toseparate various components (e.g., transistors and capacitors) from eachother or from conductive layers formed on top of them. Such dielectriclayers may also separate conductive layers (or other structures orelements) from each other. When initially formed, a dielectric layer mayassume a shape that conforms to the underlying topography. If that layeris formed on a surface that has raised and recessed features, then itcan likewise have elevated and recessed sections.

[0003] It may be desirable to planarize such a dielectric layer prior toforming subsequent layers on its surface. A chemical mechanicalpolishing (“CMP”) process may be used to planarize such a layer. Toachieve that result, it may be necessary to control such a CMP processto cause it to remove more material where the dielectric layer iselevated, and less material where the dielectric layer is recessed. Byremoving different amounts of material from different sections of thedielectric layer, a CMP process can planarize a dielectric layer, whichhad an irregular topography when deposited.

[0004] Some processes require a dielectric layer to be planarized, notto produce a substantially flat layer that covers an entire wafer, butinstead to generate a structure in which a dielectric layer fills atrench. To make such a structure, a trench is formed within a substrate,or between raised members, followed by depositing a dielectric materialover the resulting structure. A CMP process may then be used to removethe deposited material, except where it fills the trench. Measures oftenmust be taken to prevent that process from removing too much of thedielectric layer from the trench, or from removing portions of othermaterials that should be retained.

[0005] To control the CMP process, when used in such a method, it may benecessary to limit its duration, or to form a polish stop layer belowthe dielectric material. A silicon nitride layer may serve as such apolish stop layer when, for example, forming a shallow trench isolationregion in a substrate, which will separate devices to be formed onadjacent active regions. Such a polish stop layer prevents a CMP processfrom removing an excessive amount of the dielectric material (e.g.,silicon dioxide) from the trench, while protecting other portions of thesubstrate.

[0006] Current methods for controlling the CMP process, when used toplanarize a dielectric layer, may not be especially robust. Inparticular, using silicon nitride as a polish stop layer can beproblematic, if the polish rate selectivity for the dielectric layer tothe silicon nitride layer is about 4:1 or less. Because, in general, CMPprocesses are inherently nonuniform, such a polish rate selectivity mayrequire forming a thicker silicon nitride layer than would otherwise bedesired. A thicker layer may be necessary to prevent the CMP processfrom having to break through parts of it to ensure the complete removalof the dielectric layer that is deposited on the silicon nitride layer'ssurface. Integrating a thicker silicon nitride layer into the processmay decrease throughput, as it takes longer to deposit and etch athicker layer. In addition, forming a thicker layer will increase theaspect ratio (i.e., the ratio of height to width) of the trench, whichcould make it more difficult to fill the trench with the dielectriclayer.

[0007] Accordingly, there is a need for an improved method forcontrolling a CMP process that is used to remove portions of adielectric material, when making a semiconductor device. There is a needfor such a method that provides an improved polish stop layer forterminating a CMP process after it has removed the dielectric materialfrom the polish stop layer's surface. There is also a need for such amethod that enables a CMP process to effectively planarize a dielectriclayer, which has an uneven topography when initially formed. The processof the present invention provides such a method.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIGS. 1a-1 e represent cross-sections of structures that mayresult after certain steps are used, when carrying out a firstembodiment of the method of the present invention.

[0009]FIGS. 2a-2 d represent cross-sections of structures that mayresult after certain steps are used, when carrying out a secondembodiment of the method of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0010] An improved method for making a semiconductor device isdescribed. That method comprises forming a carbon doped oxide containinglayer and a dielectric layer on a substrate, such that at least part ofthe dielectric layer is located above at least part of the carbon dopedoxide containing layer. A chemical mechanical polishing process is thenapplied to remove the part of the dielectric layer that is located abovepart of the carbon doped oxide containing layer. In this method, thechemical mechanical polishing process removes the dielectric layer at asignificantly faster rate than it can remove the carbon doped oxidecontaining layer.

[0011] The method of the present invention can be used either inprocesses that form the dielectric layer on the carbon doped oxidecontaining layer, or in processes that form the carbon doped oxidecontaining layer on the dielectric layer. In either case, the part ofthe carbon doped oxide containing layer, above which at least part ofthe dielectric layer is located, may serve as a polish stop layer, whenthe chemical mechanical polishing process removes part of the dielectriclayer.

[0012] In the following description, a number of details are set forthto provide a thorough understanding of the present invention. It will beapparent to those skilled in the art, however, that the invention may bepracticed in many ways other than those expressly described here. Theinvention is thus not limited by the specific details disclosed below.

[0013]FIGS. 1a-1 e represent cross-sections of structures that mayresult after certain steps are used, when carrying out a firstembodiment of the method of the present invention. In this firstembodiment, the process of the present invention is used to form ashallow trench isolation region between the active regions of thesubstrate, where devices will be formed. Such a shallow trench isolationregion serves to separate one or more devices to be formed on a firstactive region of the substrate from one or more devices to be formed ona second active region of the substrate.

[0014]FIG. 1a illustrates structure 100, which includes substrate 101upon which are formed silicon dioxide layer 111, carbon doped oxide(“CDO”) containing layer 102, and silicon nitride layer 112. Substrate101 may comprise a silicon wafer, which has a relatively thin lightlydoped epitaxial silicon layer formed on a heavily doped bulk siliconbase. Alternatively, substrate 101 may comprise a wafer that includesother materials, for example, silicon and germanium, gallium arsenide,or indium phosphide.

[0015] When substrate 101 comprises a silicon wafer, silicon dioxidelayer 111, CDO containing layer 102, and silicon nitride layer 112 maybe formed on substrate 101 in the conventional manner. Silicon dioxidelayer 111 may, for example, be formed on substrate 101 by placingsubstrate 101 in a vertical diffusion furnace, then feeding oxygen intothe furnace while operating it at about 800° C. Silicon dioxide layer111 preferably should be no greater than about 100 angstroms thick.

[0016] CDO containing layer 102 preferably consists essentially of acarbon doped oxide that includes between about 5 and about 50 atom %carbon. Such a CDO may be deposited onto silicon dioxide layer 111(which may be considered part of the “substrate” upon which the CDOcontaining layer is formed) using conventional deposition techniques,e.g., a plasma enhanced chemical vapor deposition (“PECVD”) process.When using a PECVD process to form layer 102, gases that provide asource of silicon, oxygen, and carbon are fed into a PECVD reactor,which may then be operated at conventional temperatures, pressures, RFand power.

[0017] CDO containing layer 102 should be thick enough to serve as apolish stop layer, when a CMP process is applied to a subsequentlydeposited dielectric layer. To perform that function, CDO containinglayer 102 preferably should be between about 200 and about 2,000angstroms thick, when formed on layer 111. For certain processes, it maybe desirable to form a CDO containing layer that is between about 200and about 1,000 angstroms thick, and even more desirable to form such alayer that is less than about 500 angstroms thick.

[0018] Silicon nitride layer 112 may be formed on CDO containing layer102 using a conventional PECVD or furnace diffusion process. When aPECVD process is used, silicon nitride layer 112 may be formed on layer102 in situ, i.e., by using the same reactor chamber that was used toform layer 102. When forming layer 112 in that same chamber, the gasesused to form CDO containing layer 102 should be purged, followed byfeeding a gas stream into the chamber, which includes silane ordichlorosilane, ammonia, and nitrogen. The reactor can then be run atconventional operating conditions to form silicon nitride layer 112 onlayer 102. Alternatively, the wafer can be moved to a different chamberprior to using a PECVD process to form layer 112 on layer 102.

[0019] When furnace diffusion is used to form silicon nitride layer 112,the wafer may be placed in a diffusion furnace, then subjected to a lowpressure chemical vapor deposition process, e.g., a process that exposesthe wafer to a gas stream that contains dichlorosilane and ammonia atabout 800° C. Silicon nitride layer 112 preferably should be less thanabout 100 angstroms thick. Even such a thin layer may serve as a barrierlayer that protects CDO containing layer 102 during subsequent oxidationsteps, or photoresist ashing steps that use an oxygen plasma to removethe photoresist. Forming such a silicon nitride barrier layer on CDOcontaining layer 102 can reduce carbon depletion that might otherwiseoccur when layer 102 is exposed to oxygen or an oxygen plasma.

[0020] Another benefit to forming a thin silicon nitride layer on CDOcontaining layer 102, emanates from its giving the resulting structure asilicon nitride surface. By giving that structure such a surface, it maybe possible for the process steps, which are applied after formingsilicon nitride layer 112, to be similar to those used in currentprocesses, which use silicon nitride as the polish stop layer. Thus,forming silicon nitride layer 112 on CDO containing layer 102 shouldmake it easier to integrate layer 102 into the overall process.

[0021] For various reasons, it may be desirable to form silicon nitridelayer 112 on CDO containing layer 102, and to form silicon dioxide layer111 on substrate 101, when making a semiconductor device using themethod of the present invention. Nevertheless, a process that does notform either layer 111 or layer 112 (or both) still falls within thespirit and scope of the present invention, as long as it employs a CDOcontaining layer to control a CMP process used to remove part of adielectric layer.

[0022] After silicon nitride layer 112 is formed on CDO containing layer102, a trench will be etched through layers 112, 102 and 111, and intosubstrate 101. Conventional photolithography and etching processes maybe used to pattern, and then etch, portions of those layers, and aportion of substrate 101, to generate the trench. Layers 112, 102, and111, as well as substrate 101, may be etched in situ, i.e., with thewafer remaining in the same chamber of a plasma etcher as plasmasderived from different gas streams are used to etch the differentmaterials. For many applications, the trench preferably is less thanabout 500 nanometers deep when formed. The optimum depth for the trenchwill depend, however, upon the particular application for which theprocess of the present invention is applied.

[0023] After the trench is formed, the photoresist is removed, e.g., byusing a conventional ashing process, to generate the structureillustrated in FIG. 1b. Trench 103 is then cleaned to remove any polymerthat may have formed on sidewalls 105 of trench 103, and any residuesthat remain after the ashing step. In the resulting structure, silicondioxide layer 111, CDO containing layer 102, and silicon nitride layer112 cover first and second active regions 106, 107 of substrate 101. Inthis embodiment, active devices—e.g., transistors—will be built onactive regions 106, 107.

[0024] After photoresist residue is removed, another sequence ofcleaning steps may follow. That sequence may include a hydrofluoric acid(“HF”) dip, which cleans sidewalls 105 of trench 103 and removes a smallamount of silicon dioxide layer 111 where that layer is exposed.Removing a small amount of that layer enables a subsequent oxidationstep to create rounded edges at the trench periphery. Forming suchrounded edges may enhance device performance. After the HF dip, anadditional cleaning step (or steps) may be applied to remove particlesand organic and metallic contaminants from the wafer.

[0025] After that cleaning sequence, the resulting structure may beplaced in a furnace then exposed to oxygen at about 1000° C. Whensubstrate 101 comprises silicon, this will cause its exposed portions(i.e., sidewalls 105 and corners 113 of trench 103) tooxidize—generating rounded trench corners 114 and lining trench 103 withsilicon dioxide insulating layer 110. FIG. 1c represents the structurethat such an oxidation step produces. In this embodiment of the presentinvention, silicon nitride layer 112 protects CDO containing layer 102from exposure to oxygen during that oxidation step.

[0026] After the oxidation step, dielectric layer 108 is deposited tofill trench 103. When deposited to fill the trench, dielectric layer 108also covers silicon nitride layer 112, producing the FIG. 1d structure.Dielectric layer 108 preferably comprises silicon dioxide, but mayinclude other materials, e.g., undoped polysilicon. When layer 108comprises silicon dioxide, a conventional high density plasma (“HDP”)process (e.g., one that employs a gas stream that includes silane,oxygen and an inert gas such as argon) may be used to form that layer.(Although silane is a preferred source of silicon for such a process,other materials may be used instead, e.g., tetraethoxysilane ortetraethylorthosilicate (“TEOS”)). Such a process simultaneouslydeposits and etches the oxide, enabling trench 103 to be filled from thebottom up. As will be apparent to those skilled in the art, a typicalHDP process preferably takes place at a very low pressure (e.g., avacuum) and with a relatively high density of ions, when compared toother conventional PECVD processes.

[0027] Although dielectric layer 108 preferably is deposited onto layer112 using a HDP process, other PECVD processes may be used to form thatlayer. One such process, in which a first dielectric layer is deposited,then etched, followed by depositing a second dielectric layer, isdescribed in U.S. Pat. No. 5,719,085—assigned to this application'sassignee. By replacing a relatively thick silicon nitride polish stoplayer with a relatively thin CDO polish stop layer, the method of thepresent invention renders feasible the use of other PECVD processes toform layer 108 as the thinner polish stop layer decreases the trench'saspect ratio, making it easier to fill.

[0028] After dielectric layer 108 is formed on silicon nitride layer112, the portions of layer 108, which are located on first and secondactive regions 106, 107, must be removed. A conventional CMP process maybe used to remove layer 108 from those regions to generate the FIG. 1estructure. When such a process is applied, CDO containing layer 102 mayserve as a polish stop layer. Such a polish stop layer serves tominimize the amount of layer 108 that is removed from trench 103, andfurther ensures that the CMP process does not remove portions of thesubstrate that comprise active regions 106, 107.

[0029] In a preferred embodiment, the CMP process removes dielectriclayer 108 at a rate that is at least about 5 times as fast as the rateat which it can remove the CDO containing layer. Even more desirable isa process that removes dielectric layer 108 at a rate that is at leastabout 10 times as fast as the rate at which it can remove the CDOcontaining layer. To facilitate such a relatively high selectivity fordielectric layer 108 over CDO containing layer 102, the CMP process mayuse a slurry that comprises an abrasive and an alkaline based material.The abrasive may include a silica based material, e.g., silicon dioxide,and the alkaline based material may include a hydroxide based material,e.g., ammonium hydroxide or potassium hydroxide. Particularly preferredis a slurry that consists of fumed silica suspended in a potassiumhydroxide solution.

[0030] For processes in which polish selectivity to layer 108 over layer102 is relatively low, it may be desirable to make layer 102 thicker.Conversely, when the polish selectivity to layer 108 over layer 102 isrelatively high, it may be desirable to make layer 102 thinner. In theembodiment described here, the CMP step removes silicon nitride layer112 when removing dielectric layer 108. In other embodiments, some oflayer 112 may remain on layer 102 even after that process step.

[0031] After the structure shown in FIG. 1e is formed, CDO containinglayer 102 and silicon dioxide layer 111 must be removed from the surfaceof active regions 106 and 107 to enable devices to be formed on thosesurfaces. (If any portion of silicon nitride layer 112 remains on top oflayer 102, that remaining portion of that layer must also be removed.)Because those layers may be removed from substrate 101 usingconventional techniques that are well known to those skilled in the art,they will not be described in more detail here.

[0032] By using a CDO containing layer, instead of silicon nitride, toform the polish stop layer, the method of the present invention providesfor increased polish selectivity for the dielectric layer over thepolish stop layer. This reduces the risk that the CMP step will breakthrough the polish stop layer to the underlying substrate. In addition,this property enables a thinner polish stop layer to be used, which mayhelp increase wafer throughput and provide greater flexibility whenconsidering options for filling the trench with a dielectric layer.

[0033]FIGS. 2a-2 d represent cross-sections of structures that mayresult after certain steps are used, when carrying out a secondembodiment of the method of the present invention. FIG. 2a illustratesstructure 200, which includes substrate 201 upon which are formed raisedmembers 202 and 203. Substrate 201 may be any surface upon which variousdevices may be formed. Substrate 201 may comprise, for example, asilicon wafer, which has a relatively thin lightly doped epitaxialsilicon layer formed on a heavily doped bulk silicon base. Substrate 201may further include active and passive devices that are formed on such asilicon wafer, e.g., transistors, capacitors, resistors, diffusedjunctions, gate electrodes, local interconnects, etc . . . Substrate 201may also include insulating materials (e.g., silicon dioxide, eitherundoped or doped with phosphorus (PSG) or boron and phosphorus (BPSG);silicon nitride; silicon oxy-nitride; silicon carbide; carbon dopedoxide; an organic containing silicon oxide; or a polymer) that separatesuch active and passive devices from conductive layers that are formedon top of them, and may include various types of conductive layers.

[0034] Raised members 202, 203 may be any of a variety of structuresthat may be formed on a semiconductor device's substrate, e.g., varioustypes of dielectric or conductive elements or regions. Raised member 202is separated from raised member 203 by trench 204. For various reasons,trench 204 may be subsequently filled with dielectric layer 205, asshown in FIG. 2b. When filling trench 204, dielectric layer 205 willcover first and second raised members 202 and 203. As deposited,dielectric layer 205 includes elevated sections 208, 209 and recessedsection 210. Elevated sections 208, 209 have elevated surfaces 211, 212,and recessed section 210 has recessed surface 213.

[0035] Dielectric layer 205 preferably comprises silicon dioxide orsilicon oxyfluoride, but may include (or be made from) other materials.Layer 205 may be formed using a conventional chemical vapor depositionprocess, e.g., a conventional PECVD process. After dielectric layer 205is deposited, relatively thin CDO containing layer 214 is formed on itssurface, as shown in FIG. 2b. Layer 214 preferably consists essentiallyof a carbon doped oxide that includes between about 5 and about 50 atom% carbon, and may be formed using conventional PECVD techniques. Layer214 may be deposited on layer 205 in situ, i.e., without having toremove the wafer from the chamber that was used to deposit layer 205.

[0036] In the resulting structure, CDO containing layer 214 coverselevated surfaces 211, 212 and recessed surface 213 of dielectric layer205. CDO containing layer 214 should be thick enough to ensure that asubsequent CMP polishing process can generate a more planar surface fordielectric layer 205 than could be generated in the absence of layer214. To perform that function, CDO containing layer 214 preferably isbetween about 100 and about 2,000 angstroms thick, when formed ondielectric layer 205. The optimum thickness for layer 214 will dependupon the particular application for which the described method isapplied.

[0037] After CDO containing layer 214 is formed on dielectric layer 205,the portions of layer 205 that lie above first and second raised members202, 203 are removed. A conventional CMP process may be used to performthat function. When such a process is applied, it initially removes CDOcontaining layer 214, where formed on elevated surfaces 211, 212 ofdielectric layer 205, to generate the FIG. 2c structure. Because thepolishing pad will conform to the topography of the surface to bepolished, the polishing action will simultaneously remove layer 214 fromthe side and from the top of elevated sections 208, 209 causing taperedextensions 206 to form.

[0038] Next, elevated sections 208, 209 of dielectric layer 205 areremoved, followed by removing CDO containing layer 214, where formed onrecessed surface 213 of dielectric layer 205. After the remainder oflayer 214 is removed from the surface of dielectric layer 205, the CMPprocess removes recessed section 210 from dielectric layer 205 toproduce the FIG. 2d structure.

[0039] As FIGS. 2b-2 d illustrate, in this embodiment, the CMP processremoves dielectric layer 205 from the surfaces of raised members 202,203 to generate a substantially planar surface for the portion ofdielectric layer 205 that remains inside trench 204. As shown in FIG.2d, that substantially planar surface is substantially flush with thesurfaces of raised members 202, 203. Although this embodiment polishesdielectric layer 205 down to the surfaces of raised members 202, 203,alternative embodiments may generate a substantially planar surface forlayer 205 that is located above those raised members. Such a planarsurface may lie at the level of the lower sections of layer 214, withthose sections of layer 214 performing a polish stop function, or liebelow that level, e.g., when removing all of layer 214 before generatinga planar surface that is located above the raised members.

[0040] In a preferred embodiment, the CMP process used to remove CDOcontaining layer 214 and part of dielectric layer 205 removes dielectriclayer 205 at a rate that is at least about 5 times, and more preferablyat least about 10 times, as fast as the rate at which it removes the CDOcontaining layer. To facilitate such a relatively high selectivity fordielectric layer 205 over CDO containing layer 214, the CMP process mayuse a slurry that comprises an abrasive and an alkaline based material,e.g., a slurry that consists of fumed silica suspended in a potassiumhydroxide solution. Layers 214 and 205 may be removed using a singlecontinuous CMP process, or alternatively, by modifying the CMP processas the polishing process works its way down through those layers.

[0041] By forming a CDO containing layer on top of a dielectric layer,this embodiment of the present invention enables a CMP process toplanarize a dielectric layer, which has an uneven topography wheninitially formed. This result may be achieved because the CDO anddielectric layers polish at different rates. Because the CMP processremoves the carbon doped oxide at a much slower rate than it removes thedielectric layer, elevated sections 208, 209 of dielectric layer 205 maybe removed, while recessed section 210 remains protected by CDOcontaining layer 214. Removing elevated sections 208, 209, whileretaining recessed section 210, may produce a structure that has asubstantially planar surface. The remainder of layer 214, and recessedsection 210, can then be removed, if desired, to generate the FIG. 2dstructure.

[0042] Features shown in the above referenced drawings are not intendedto be drawn to scale, nor are they intended to be shown in precisepositional relationship. Additional process steps that may be used tomake the embodiments described above have been omitted when not usefulto describe aspects of the present invention.

[0043] Although the foregoing description has specified a method forforming a semiconductor device that uses certain materials and processsteps, those skilled in the art will appreciate that many modificationsand substitutions may be made. Accordingly, it is intended that all suchmodifications, alterations, substitutions and additions be considered tofall within the spirit and scope of the invention as defined by theappended claims.

What is claimed is:
 1. A method for forming a semiconductor devicecomprising: forming a carbon doped oxide containing layer and adielectric layer on a substrate, such that at least part of thedielectric layer is located above at least part of the carbon dopedoxide containing layer; and then applying a chemical mechanicalpolishing process to remove the part of the dielectric layer that islocated above the part of the carbon doped oxide containing layer, thechemical mechanical polishing process removing the dielectric layer at asignificantly faster rate than it can remove the carbon doped oxidecontaining layer.
 2. The method of claim 1 wherein the dielectric layeris formed on the carbon doped oxide containing layer.
 3. The method ofclaim 1 wherein the carbon doped oxide containing layer is formed on thedielectric layer.
 4. The method of claim 1 wherein the part of thecarbon doped oxide containing layer, above which at least part of thedielectric layer is located, serves as a polish stop layer, when thechemical mechanical polishing process removes part of the dielectriclayer.
 5. A method for forming a semiconductor device comprising:forming a carbon doped oxide containing layer and a dielectric layer ona substrate, the dielectric layer filling a trench; and then applying achemical mechanical polishing process to remove the dielectric layerwhere located outside of the trench, the chemical mechanical polishingprocess removing the dielectric layer at a significantly faster ratethan it can remove the carbon doped oxide containing layer.
 6. Themethod of claim 5 wherein the dielectric layer is formed on the carbondoped oxide containing layer.
 7. The method of claim 5 wherein thecarbon doped oxide containing layer is formed on the dielectric layer.8. The method of claim 5 further comprising using a high density plasmaprocess to generate the dielectric layer, and wherein the dielectriclayer comprises silicon dioxide.
 9. A method for forming a semiconductordevice comprising: forming within a substrate a shallow trench isolationregion, which will separate a first device to be formed on a firstactive region of the substrate from a second device to be formed on asecond active region of the substrate, by: forming a carbon doped oxidecontaining layer on the substrate; removing a portion of the carbondoped oxide containing layer and a portion of the underlying substrateto form a trench within the substrate, the carbon doped oxide containinglayer remaining on the first and second active regions of the substrate;filling the trench with a dielectric layer, the dielectric layercovering the carbon doped oxide containing layer where that layer coversthe first and second active regions of the substrate; and applying achemical mechanical polishing process to remove the dielectric layerfrom the surface of the carbon doped oxide containing layer.
 10. Themethod of claim 9 wherein the dielectric layer comprises silicondioxide.
 11. The method of claim 10 wherein the carbon doped oxidecontaining layer, when formed on the substrate, is between about 200 andabout 2,000 angstroms thick.
 12. The method of claim 11 wherein thechemical mechanical polishing process can remove the dielectric layer ata rate that is at least about 5 times as fast as the rate at which itcan remove the carbon doped oxide containing layer.
 13. The method ofclaim 12 further comprising lining the trench with a silicon dioxidelayer prior to filling the trench with the dielectric layer.
 14. Themethod of claim 13 further comprising forming a silicon nitride layer onthe carbon doped oxide containing layer after forming the carbon dopedoxide containing layer on the substrate and before forming the trench.15. The method of claim 14 wherein the silicon nitride layer is lessthan about 100 angstroms thick, when formed on the carbon doped oxidecontaining layer.
 16. A method for forming a semiconductor devicecomprising: forming a dielectric layer on a substrate, the dielectriclayer having an elevated section and a recessed section; forming acarbon doped oxide containing layer on the dielectric layer; andapplying a chemical mechanical polishing process to remove part of thedielectric layer and at least part of the carbon doped oxide containinglayer, the chemical mechanical polishing process removing the dielectriclayer at a significantly faster rate than it removes the carbon dopedoxide containing layer.
 17. The method of claim 16 wherein the chemicalmechanical polishing process removes portions of the dielectric layerand at least portions of the carbon doped oxide containing layer togenerate a more planar surface.
 18. The method of claim 17 wherein thechemical mechanical polishing process removes the carbon doped oxidecontaining layer, where formed on the elevated section of the dielectriclayer, then removes the elevated section of the dielectric layer, thenremoves the carbon doped oxide containing layer, where formed on therecessed section of the dielectric layer, then removes the recessedsection of the dielectric layer to generate the more planar surface. 19.A method for forming a semiconductor device comprising: forming firstand second raised members on a substrate, the first raised member beingseparated from the second raised member by a trench; filling the trenchwith a dielectric layer, the dielectric layer covering the first andsecond raised members when filling the trench, and having elevatedsections with elevated surfaces where formed on the first and secondraised members, and a recessed section with a recessed surface wherefilling the trench; forming a carbon doped oxide containing layer on thedielectric layer; and applying a chemical mechanical polishing processto remove part of the dielectric layer and at least part of the carbondoped oxide containing layer, the chemical mechanical polishing processremoving the dielectric layer at a significantly faster rate than itremoves the carbon doped oxide containing layer.
 20. The method of claim19 wherein the chemical mechanical polishing process removes the carbondoped oxide containing layer, where formed on the elevated surfaces ofthe dielectric layer, then removes the elevated sections of thedielectric layer, then removes the carbon doped oxide containing layer,where formed on the recessed surface of the dielectric layer, thenremoves the recessed section of the dielectric layer to generate asubstantially planar surface for the portion of the dielectric layerthat remains inside the trench, with that substantially planar surfacebeing substantially flush with the surfaces of the first and secondraised members.